According to Jeff Dean on X, Google introduced TPU 8t for large-scale training and inference with a pod size of 9,600 chips delivering about 121 exaflops FP4 per pod, roughly 3X the FP4 performance of Ironwood’s 42.5 exaflops per pod (as reported in Dean’s April 23, 2026 post). According to Jeff Dean, the FP4-focused uplift targets high-throughput inference and frontier model training, signaling lower cost per token and faster time-to-train for multi-trillion parameter workloads. As reported by Jeff Dean, the pod-level scaling implies denser datacenter footprints and higher utilization for Google Cloud customers building LLMs and VLMs, creating business opportunities in model serving, batch inference, and fine-tuning at scale.

According to Sundar Pichai on Twitter, Google introduced TPU 8t optimized for training and TPU 8i optimized for inference, signaling a clear split in accelerator design for distinct AI workloads. As reported by Pichai, the 8t variant targets high-throughput model training, while 8i focuses on low-latency, cost-efficient serving, which implies tailored silicon pathways for scaling foundation model training and production inference. According to the tweet, this differentiation can help enterprises reduce total cost of ownership by matching hardware to workload phases, enabling faster time-to-value for generative AI deployments. As reported by the original tweet, the announcement suggests opportunities for MLOps teams to streamline pipelines—training on 8t and deploying on 8i—while model providers and SaaS platforms can optimize SLAs and margins through workload-aware scheduling and autoscaling.